I assume ema means the original line, e.g.
z= (a or b ) and (c and (d or f))
or, as a start,
z= a or b
.
It sounds this has less to do with Verilog itself and more so just how to build an expression tree for logic gates.
As I said earlier, I suggest doing something akin to the shunting yard algorithm.
Start with the simpler equation first: a or b.
But for the more complicated equation, you would split it up into its tokens
e.g. {
(, a, or, b, ), and, (, c, and, (, d, or, f, ), )
}
Then, you start to apply (a modified, perhaps simpler, version of) the shunting-yard algorithm
https://en.wikipedia.org/wiki/Shunting-yard_algorithm
This will transform your equation as you see fit into reverse-Polish notation, and from there you can combine both binary operands as children of the operator parent. (Or, you could modify it to directly build the tree, I suppose.)
e.g.
For
a or b
, you push a, push b, and then once you see an operator, you consume the operator and pop-off the previous two tokens.
So, a or b becomes
a, b, or
, and basically:
- first operand becomes left child
- second operator become right leaf
- operator (or) becomes parent leaf.
I'm probably not explaining it the best, it takes some care to make sure you get it right with parentheses; I do suggest reading the Wikipedia article or searching for other articles on mathematical expression trees.